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High performance bipolar FPLAsTAKEDA, T; MATSUHIRO, K; SUZUKI, M et al.Review of the electrical communication laboratories. 1983, Vol 31, Num 4, pp 566-575, issn 0029-067XArticle

IUMRS-ICEM-2010. Materials and Devices for Future Logic TechnologyCHOI, Rino; CHEOL SEONG HWANG; YOUNG-BAE PARK et al.Microelectronic engineering. 2012, Vol 89, issn 0167-9317, 143 p.Conference Proceedings

Multi-valued logic systemsHAWKEN, R. E.International journal of electronics. 1989, Vol 67, Num 5, issn 0020-7217, 142 p.Serial Issue

Multilevel logical networksKARPOVSKY, M.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 215-226, issn 0018-9340Article

An algorithm for the partitioning of logic circuitsROBERTS, M. W; LALA, P. K.IEE proceedings. Part E. Computers and digital techniques. 1984, Vol 131, Num 4, pp 113-118, issn 0143-7062Article

Hard magnetic cylindrical domains (HMD) as elements of multistate logicSZKODNY, T.Bulletin of the Polish Academy of Sciences. Technical sciences. 1984, Vol 32, Num 5-6, pp 333-339, issn 0239-7528Article

ATILA, a program to generate test patterns for scan testable logicSMITH, P. J.GEC journal of research. 1988, Vol 6, Num 3, pp 147-151, issn 0264-9187Article

Development of a user friendly gate-level logic simulatorSTIGALL, P. D; KUMAR SHIV.Computers & electrical engineering. 1987, Vol 13, Num 3-4, pp 147-167, issn 0045-7906Article

Evaluating the signal-reliability of logic circuitsKYUNG-SHIK KOH.IEEE transactions on reliability. 1985, Vol 34, Num 3, pp 233-235, issn 0018-9529Article

Optimal shut-down logic for protective systemsKOHDA, T; KUMAMOTO, H; INOUE, K et al.IEEE transactions on reliability. 1983, Vol 32, Num 1, pp 26-29, issn 0018-9529Article

Hybrid integratorKAWABE, S; OHNIWA, K.Electrical engineering in Japan. 1983, Vol 103, Num 6, pp 134-140, issn 0424-7760Article

Einsatzerfahrungen und Weiterentwicklung des Gate-Array-Entwurfssystems PC-GAD = Experiences obtained and future development of the gate assay design system PC-GADPAULIUK, J.Wissenschaftliche Zeitschrift der Technischen Universität Karl-Marx-Stadt. 1989, Vol 31, Num 4, pp 521-527, issn 0863-0615, 7 p.Article

Switching in NERFET circuitsKASTALSKY, A; LURYI, S; GOSSARD, A. C et al.IEEE electron device letters. 1985, Vol 6, Num 7, pp 347-349, issn 0741-3106Article

Iterative exhaustive pattern generation for logic testingTANG, D. T; CHEN, C. L.IBM journal of research and development. 1984, Vol 28, Num 2, pp 212-219, issn 0018-8646Article

A method for generating weighted random test patternsWAICUKAUSKI, J. A; LINDBLOOM, E; EICHELBERGER, E. B et al.IBM journal of research and development. 1989, Vol 33, Num 2, pp 149-161, issn 0018-8646, 13 p.Article

Parity predictor for shifting-output addersVASSILIADIS, S; PUTRINO, M; SCHWARZ, E. M et al.Electronics Letters. 1989, Vol 25, Num 6, pp 422-424, issn 0013-5194, 3 p.Article

Error-sevure and error-propagating concepts for strongly fault-secure systemsNANYA, T; KAWAMURA, T.Systems and computers in Japan. 1987, Vol 18, Num 3, pp 11-18, issn 0882-1666Article

Fine Entwurfsstrategie für den logischen Schaltungsentwurf = Une stratégie pour le dessin logique des circuits = A strategy for the logical design of circuitsBOCHMANN, D; POSTHOFF, C.Wissenschaftliche Zeitschrift der Technischen Hochschule Karl-Marx-Stadt. 1984, Vol 25, Num 6, pp 805-813, issn 0372-7610Article

PLAS ZUR LOESUNG VON VERTEILUNGSAUFGABEN. = LES RESEAUX LOGIQUES PROGRAMMABLES POUR LA RESOLUTION DES PROBLEMES DE REPARTITIONEICHHOFER H; TIMM V.1977; ELEKTRONIK; DTSCH.; DA. 1977; VOL. 26; NO 6; PP. 59-76 (6P.); BIBL. 8 REF.Article

A HEURISTIC TEST-PATTERN GENERATOR FOR PROGRAMMABLE LOGIC ARRAYSEICHELBERGER EB; LINDBLOOM E.1980; I.B.M. J. RES. DEVELOP.; USA; DA. 1980; VOL. 24; NO 1; PP. 15-23; BIBL. 10 REF.Article

CONCURRENT ERROR DETECTION AND TESTING FOR LARGE PLA'SKHAKBAZ J; MCCLUSKEY EJ.1982; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 2; PP. 386-394; BIBL. 22 REF.Article

Technique to study multiple-valued logic in courses on modern logic design of discrete devicesLEVASHENKO, V; ZAITSEVA, E; SANKO, A et al.International conference on new information technologies in education. 1996, pp 329-338, isbn 83-86359-44-7Conference Paper

High-speed divider using GaAs ECL/CML gate arrayTOPHAM, P. J; PARTON, J. G; GOLDER, M. J et al.Electronics Letters. 1989, Vol 25, Num 7, pp 432-433, issn 0013-5194, 2 p.Article

Design-performance trade-offs in CMOS-domino logicOKLOBDZIJA, V. G; MONTOYE, R. K.IEEE journal of solid-state circuits. 1986, Vol 21, Num 2, pp 304-306, issn 0018-9200Article

Low-power Si-bipolar multi-Gbit/s logics having the same function as ECL100K familyYAMANAKA, N; MIYANAGA, H; YAMAMOTO, Y et al.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1986, Vol 69, Num 10, pp 1068-1071, issn 0387-236XArticle

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